In constructing a gate array, a semiconductor device is formed as a "base cell" comprising standardized segments of polysilicon configured to function as P-channel and N-channel transistors. The base cell is designed to make processing of a semiconductor device standard prior to the metalization level(s). With this design, it is possible to construct the semiconductor device simply by placing contacts, vias and metal leads at predetermined points on the prefabricated cell. This reduces costs in device fabrication by minimizing unique processing steps usually necessary for device fabrication. This type of process has significant economic benefits, because it permits the standardization of cell configurations and eliminates the need for specialized or uniquely designed gate array cells. Certain problems exist, however, when using a base cell for producing some semiconductor device functions. One significant limitation is that, because the gate array base cell is already designed on the semiconductor wafer, functional flexibility of these cells is minimal and often much less than that desired for particular applications.
Traditionally, in the design of a CMOS gate array, it has been recognized that the gate array performance is frequently less than that of specially designed devices. Recognizing this problem, gate array base cell designers may design an N-channel transistor and a P-channel transistor each having the same size and pre-determined routable connection points or targets on the polysilicon, N-moat, or P-moat layers that comprise the transistors. Thus, for one type of gate array formed from a base cell, the P-channel transistor and N-channel transistor have their gates connected together, but with no connection between their source/drains.
The typical gate array function is a two-input gate such as a NAND-gate and the typical base cell is designed as a two-stripe configuration. A stripe is a N-channel and P-channel transistor with a common gate of polysilicon. In the two-stripe configuration, the N-channel transistors share a common source/drain and the P-channel transistors share a common source/drain.
For a gate array, the size of the P-channel and N-channel portions of each stripe must be sufficiently large to permit a desired number of targets on the respective layers of polysilicon NMOT and PMOT for the placement of connects, vias, and metal to connect the various base cell portions. If the P-channel or N-channel is too small, an insufficient number of target points will exist to permit the routing of the metal leads for flexible interconnection of the gate array base cell for its intended application. One characteristic of P-channel transistors is that they produce less transconductance than the N-channel transistor for the same channel size. Thus, for the same transistor size, the N-channel transistor produces more current flow than does the P-channel transistor. This means that for the same size transistors driving a node, the P-channel transistor is slower to pull the voltage more positive than the N-channel is to pull the voltage low on a given node.
Some gate array base cell designs include designs for memory cells to perform memory functions within the base cell gate array. There are two known ways to achieve this result. First, it is possible to design the base cell gate array and then substitute, at desired points, memory cells capable of performing memory functions. This, in essence, results in a custom configuration of a gate array capable of performing memory functions. The most important limitation associated with this concept is its need for custom design and the expense associated with such design. Furthermore, it is even questionable whether there still exists a true gate array by definition of same using this technique.
Another known way to achieve the desired result of having a memory function on the base cell gate array is to design the memory cells in the base cell array as part of the standard design of the gate array. This design, however, also has significant drawbacks. When implementing a memory function in a CMOS base cell gate array, the simplest way of doing so is to use two inverters so connected that the output of each drives the input of the other. With this design, multiple memory cells are connected to sense/drive circuits be two complementary sense lines, one being labeled positive and the other negative. Each memory cell includes a select mechanism that permits the connection of only one memory cell to the sense/drive lines at a time. The best way to achieve this result is to design an N-channel transistor to connect the memory cell inverters to the sense lines.
In using the N-channel transistors to connect the memory cell inverters to the sense lines, an undesirable property of these transistors called "body effect" comes into play during a write cycle which limits the current transfer capability of the N-channel transistor. The larger the P-channel transistor, the larger must be the current drive required to write to it, therefore the larger must be the N-channel transistors used as select elements. However, the larger the N-channel select transistors, the larger the select drivers. Ultimately this tends to cause increased power dissipation and reduced circuit speeds.
For logic functions however, it is desired that the P-channel transistors exhibit equal transconductance to that of the N-channel transistors. But, polysilicon doped to perform in a P-channel transistor exhibits less transconductance per unit area than does an N-channel transistor. This necessarily means that the P-channel transistor must be larger than the N-channel transistor to achieve maximum performance.
Since all prior base cell configurations use a single P-channel transistor and a single N-channel transistor per stripe, it is not possible to adequately satisfy the needs of performing both the logic function and memory cell function with known base cells.
As a result, there is no known practical way to implement a memory function on a gate array base cell with generally acceptable speed, circuit density and reliability characteristics or any guarantee of manufacturability without reducing the size of the P-channel transistors. This results, however, in the limitation that the smaller P-channel transistors are undesirable for regular or normal standard logic functions that the base cell gate array performs. Basically, then, the memory function is the principal function of a gate array for which a small P-channel is desired. Most other functions require a large P-channel for proper operation.
Thus, there is a need for a gate array base cell that overcomes the limitations associated with existing base cell designs when the application for the base cell includes memory functions.
There is a need for a gate array base cell design that permits the economical design of gate arrays that provide memory functions.
There is a need for a gate array base cell design that permits the selectable use of the gate array for logic functions as well as memory functions.